ELBRUS 48XMN
SILICON AT THE SPEED OF SOFTWARE
SILICON AT THE SPEED OF SOFTWARE
INTRODUCE ELBRUS 48XMN
Key Features
-
Architecture: “RV32IMACF”
- 32-bit RISC-V with 32 integer registers (I extension)
- Integer multiplication and division (M extension)
- Atomic operation support (A extension)
- Compressed mode for better code density (C extension)
- Optional IEEE 754-2008 compliant single precision floating point (F extension)
- Single instruction issue
- Machine, Supervisor and User modes
- 10 stage in-order pipeline
- Advanced branch predictor: BTB, BHT, RAS
- Sv32 Virtual Memory support
- 4 to 32 KiB, 2 to 8-way L1 I-cache
- 4 to 32 KiB, 2 to 8-way L1 D-cache
- Integrated 128 KiB to 2 MiB L2 Cache
- Platform Level Interrupt Controller (PLIC): 127 interrupts with 8 priority levels
- Multi-Core Local Interruptor (CLINT): timer + software interrupts
Interrupts:
- Integrated debug controller
- AXI system interface
- AXI peripheral interface
- AXI front-port interface for peripherial coherent access
- 1.6 DMIPS/MHz
- 2.9 CoreMark/MHz
- 1 GHz (TSMC, 40nm G, SSG corner)
- 1.2 GHz (TSMC, 28nm HPC+, SSG corner)
Performance:
Frequency:
SMP support and accelerator coherency
48XMN has up to 4 cores, each with an L1 caches and a single shared L2 cache implementing fully coherent memory system. Additional coherency controller provides coherent access for accelerators via AXI front port to cached memory ranges simplifies software development and improves performance.
Development Tools
Complete set of RISC-V tools for fast and convenient software development. Compatible with upstream standard development and debug tools: OpenOCD, GCC, GDB, Eclipse. Elbrus also provides pre-configured Eclipse-based IDE with prebuilt toolchain and example projects for easy development start.
EXAMPLE USE CASES
include: smartwatches, portable instruments, wall-mounted displays and vending machines.