ELBRUS 48XIM
SILICON AT THE SPEED OF SOFTWARE
Design Arm amd RISC Cpu in very short time
INTRODUCE ELBRUS 48XIM
Key Features
Architecture: “RV64GC”
- 64-bit RISC-V with 32 integer registers (I extension)
- Integer multiplication and division (M extension)
- Atomic operation support (A extension)
- Compressed mode for better code density (C extension)
- IEEE 754-2008 compliant single and double precision floating point (F+D extensions)
- Up to 4 cores in complex
- Machine, Supervisor and User modes
- 10 stage out-of-order pipeline
- Advanced branch predictor: BTB, BHT, RAS
- Sv39 Virtual Memory support
- 32 KiB 8-way L1 I-cache
- 32 KiB 8-way L1 D-cache
- Integrated 1-2 MiB L2 Cache
- Integrated debug controller
- AXI system interface
- AXI peripheral interface
- AXI front-port interface for accelerator coherent access
Performance:
-
- 3.58 DMIPS/MHz
- 5.36 CoreMark/MHz
- 4.6 SPEC2006 INT/GHz
Frequency:
- 1 GHz (TSMC, 40nm G, SSG corner)
- 1.2 GHz (TSMC, 28nm HPC+, SSG corner)
Peripherial and accelerator coherency
48Xim includes coherency controller which provides coherent access for peripheral devices and accelerators via AXI front port to cached memory ranges simplifies software development and improves performance. Design Arm amd RISC Cpu in very short time.
Development Tools
Complete set of RISC-V tools for fast and convenient software development. Compatible with upstream standard development and debug tools: OpenOCD, GCC, GDB, Eclipse. Elbrus also provides pre-configured Eclipse-based IDE with prebuilt toolchain and example projects for easy development start.
EXAMPLE USE CASES
Security Device,POS,Secure Cash registry